I. Field of the Disclosure
The technology of the disclosure relates to temperature compensating adaptive voltage scalers (AVSs), systems, and methods for optimizing power consumption in a functional circuit(s).
II. Background
Synchronous digital circuits, such as central processing units (CPUs) or digital signal processors (DSPs) for example, require a clock signal to coordinate timing of logic in the circuit. The frequency of the clock signal controls the switching speed or rate of the logic and thus the performance of the circuit. There is a relationship between operating frequency and the voltage level powering a circuit. An increase in operating frequency increases the minimum voltage level required to power the circuit for proper operation. Thus, an increase in operating frequency generally results in more power consumption. Power consumption can be decreased by lowering the voltage level. However, a decrease in voltage level decreases the maximum operating frequency possible for the circuit. The voltage level can be decreased until a minimum threshold voltage level for the circuit necessary for proper operation is reached.
While it is generally desired to maximize performance of a circuit by maximizing the operating frequency, there may be times when maximizing the operating frequency is not required or desired. In this instance, the voltage level powering the circuit could be reduced to conserve power. In this regard, a dynamic voltage scaler (DVS) can be employed. The DVS can control a clock generator to produce a clock signal for the circuit at a desired operating frequency. The DVS can adjust the voltage to a minimum voltage level at a given operating frequency to conserve power while maintaining proper circuit operation.
Other factors can raise the minimum voltage level required to power a circuit at a given operating frequency. For example, variability in nanometer integrated circuit (IC) processes used to manufacture synchronous digital circuits and their components can cause delay variations. Environmental conditions, such as operating temperature and aging effect of transistors, can affect propagation delay. Voltage levels supplied by voltage supplies can be momentarily lowered due to variations in current draw, thus momentarily lowering performance. In this regard, a DVS may be configured to control the minimum voltage level for the circuit according to worst case delay scenarios to ensure proper circuit operation, when in actuality, worst case delay scenarios are not present at all times. When worst case delay scenarios are not present, the voltage level could be lowered and the circuit operates properly. The difference between the worst case minimum voltage level and the actual minimum voltage level required to power a circuit for a given operating frequency at a given time is known as voltage or power margin. Voltage margin represents consumed power that did not have to be consumed for a circuit to properly operate at a given operating frequency.